๐Ÿง  Accelerator

TVM ์ƒ์„ธ

๊ฐœ์š”

Apache TVM(Tensor Virtual Machine)์€ ๋‹ค์–‘ํ•œ ํ•˜๋“œ์›จ์–ด ๊ฐ€์†๊ธฐ์—์„œ ๊ณ ์„ฑ๋Šฅ ๋จธ์‹ ๋Ÿฌ๋‹ ์‹คํ–‰์„ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜๋Š” ์˜คํ”ˆ์†Œ์Šค ๋”ฅ ๋Ÿฌ๋‹ ์ปดํŒŒ์ผ๋Ÿฌ ์Šคํƒ์ด๋‹ค. 2017๋…„์— ์†Œ๊ฐœ๋œ ์ดํ›„ Apache ์†Œํ”„ํŠธ์›จ์–ด ์žฌ๋‹จ ์‚ฐํ•˜์—์„œ ํ™œ๋ฐœํžˆ ๊ฐœ๋ฐœ๋˜๊ณ  ์žˆ์œผ๋ฉฐ, GPU(CUDA, OpenCL), CPU(LLVM), TPU, NPU ๋“ฑ ๊ด‘๋ฒ”์œ„ํ•œ ํ•˜๋“œ์›จ์–ด๋ฅผ ์ง€์›ํ•œ๋‹ค. TVM์€ ํ”„๋ ˆ์ž„์›Œํฌ ๋…๋ฆฝ์ ์ธ IR(Intermediate Representation)์„ ํ†ตํ•ด PyTorch, TensorFlow, ONNX ๋“ฑ ๋‹ค์–‘ํ•œ ML ํ”„๋ ˆ์ž„์›Œํฌ์˜ ๋ชจ๋ธ์„ ์ˆ˜์šฉํ•˜๊ณ , ํ•˜๋“œ์›จ์–ด์— ํŠนํ™”๋œ ๊ณ ์„ฑ๋Šฅ ์ปค๋„์„ ์ž๋™์œผ๋กœ ์ƒ์„ฑํ•œ๋‹ค.

TVM์˜ ํ•ต์‹ฌ ์„ค๊ณ„ ์ฒ ํ•™์€ "์—”๋“œํˆฌ์—”๋“œ ์ตœ์ ํ™”(end-to-end optimization)"์ด๋‹ค. ๋ชจ๋ธ ์ˆ˜์ค€์˜ ๊ทธ๋ž˜ํ”„ ์ตœ์ ํ™”๋ถ€ํ„ฐ ์ปค๋„ ์ˆ˜์ค€์˜ ๋ฃจํ”„ ํƒ€์ผ๋ง, ๋ฒกํ„ฐํ™”, ์Šค๋ ˆ๋“œ ๋ฐ”์ธ๋”ฉ๊นŒ์ง€ ํ•˜๋‚˜์˜ ํ†ตํ•ฉ ํŒŒ์ดํ”„๋ผ์ธ์—์„œ ์ฒ˜๋ฆฌํ•œ๋‹ค. ์ตœ๊ทผ TVM์€ ๊ณ ์ˆ˜์ค€ ๊ทธ๋ž˜ํ”„ ์ถ”์ƒํ™”๋ฅผ ๋‹ด๋‹นํ•˜๋Š” Relax์™€ ์ €์ˆ˜์ค€ ํ…์„œ ํ”„๋กœ๊ทธ๋žจ์„ ๋‹ด๋‹นํ•˜๋Š” TensorIR์˜ ์ด์ค‘ IR ๊ตฌ์กฐ๋ฅผ ์ฑ„ํƒํ•˜์—ฌ, ๊ทธ๋ž˜ํ”„-์ปค๋„ ์ˆ˜์ค€ ๊ต์ฐจ ์ตœ์ ํ™”๋ฅผ ์ง€์›ํ•œ๋‹ค.

ํ•ต์‹ฌ ๊ฐœ๋…

TVM ์Šคํƒ ์•„ํ‚คํ…์ฒ˜

TVM Stack Architecture

TVM ์Šคํƒ์€ ํฌ๊ฒŒ ๋„ค ๊ฐ€์ง€ ๊ณ„์ธต์œผ๋กœ ๊ตฌ์„ฑ๋œ๋‹ค:

๊ณ„์ธต ๋ชจ๋“ˆ ์„ค๋ช…
ํ”„๋ก ํŠธ์—”๋“œ Relax Frontend ONNX, PyTorch, TensorFlow ๋ชจ๋ธ ์ž„ํฌํŠธ
๊ณ ์ˆ˜์ค€ IR Relax ๊ทธ๋ž˜ํ”„ ์ˆ˜์ค€ ์ถ”์ƒํ™”, ์—ฐ์‚ฐ ์œตํ•ฉ, ์ƒ์ˆ˜ ํด๋”ฉ
์ €์ˆ˜์ค€ IR TensorIR (tirx/s_tir) ๋ฃจํ”„ ํƒ€์ผ๋ง, ์Šค์ผ€์ค„๋ง, ๋ฒกํ„ฐํ™”
๋ฐฑ์—”๋“œ Target/Codegen LLVM, CUDA, OpenCL ๋“ฑ ํ•˜๋“œ์›จ์–ด๋ณ„ ์ฝ”๋“œ ์ƒ์„ฑ

IRModule: ํ•ต์‹ฌ ๋ฐ์ดํ„ฐ ๊ตฌ์กฐ

TVM์˜ ๋ชจ๋“  ๋ณ€ํ™˜์€ IRModule์„ ์ค‘์‹ฌ์œผ๋กœ ์ด๋ฃจ์–ด์ง„๋‹ค. IRModule์€ ๋‘ ์ข…๋ฅ˜์˜ ํ•จ์ˆ˜๋ฅผ ํฌํ•จํ•œ๋‹ค:

  • relax.Function: ๊ณ ์ˆ˜์ค€ ํ•จ์ˆ˜ํ˜• ํ”„๋กœ๊ทธ๋žจ ํ‘œํ˜„. ๊ทธ๋ž˜ํ”„ ๊ตฌ์กฐ๋ฅผ ๊ฐ€์ง€๋ฉฐ, ์ œ์–ด ํ๋ฆ„๊ณผ ๋ณต์žกํ•œ ๋ฐ์ดํ„ฐ ๊ตฌ์กฐ๋ฅผ ์ง€์›ํ•œ๋‹ค. ๋ชจ๋ธ์ด๋‚˜ ์„œ๋ธŒ๊ทธ๋ž˜ํ”„์— ๋Œ€์‘ํ•œ๋‹ค.
  • tirx.PrimFunc: ์ €์ˆ˜์ค€ ํ…์„œ ํ”„๋กœ๊ทธ๋žจ ํ‘œํ˜„. ๋ฃจํ”„ ์ค‘์ฒฉ, ๋‹ค์ฐจ์› ๋กœ๋“œ/์Šคํ† ์–ด, ์Šค๋ ˆ๋”ฉ, ๋ฒกํ„ฐ/ํ…์„œ ๋ช…๋ น์–ด๋ฅผ ํฌํ•จํ•œ๋‹ค. ์œตํ•ฉ๋œ ์ปค๋„ ํ•˜๋‚˜๋ฅผ ๋‚˜ํƒ€๋‚ธ๋‹ค.

์ปดํŒŒ์ผ ๊ณผ์ •์—์„œ ๋ชจ๋“  relax ์—ฐ์‚ฐ์€ tirx.PrimFunc์ด๋‚˜ TVM PackedFunc์œผ๋กœ ๋กœ์–ด๋ง(lowering)๋˜๋ฉฐ, relax ์—ฐ์‚ฐ ํ˜ธ์ถœ์€ ์ €์ˆ˜์ค€ ํ•จ์ˆ˜ ํ˜ธ์ถœ(์˜ˆ: R.call_tir)๋กœ ๋ณ€ํ™˜๋œ๋‹ค.

TVMScript

TVMScript๋Š” Python ๊ธฐ๋ฐ˜ DSL๋กœ, TVM IR๋ฅผ ๊ธฐ์ˆ ํ•  ์ˆ˜ ์žˆ๊ฒŒ ํ•œ๋‹ค. @I.ir_module, @T.prim_func, @R.function ๋ฐ์ฝ”๋ ˆ์ดํ„ฐ๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ Python ๋ฌธ๋ฒ•์œผ๋กœ IRModule์„ ์ •์˜ํ•˜๋ฉฐ, ํŒŒ์ด์ฌ ์ธํ„ฐํ”„๋ฆฌํ„ฐ๊ฐ€ ์•„๋‹Œ ํŒŒ์„œ๋ฅผ ํ†ตํ•ด TVM IR๋กœ ๋ณ€ํ™˜๋œ๋‹ค. ๋ชจ๋“  IRModule์€ TVMScript๋กœ ์—ญ์ง๋ ฌํ™”(roundtrip)๊ฐ€ ๊ฐ€๋Šฅํ•˜๋‹ค.

TensorIR (tirx + s_tir)

TensorIR์€ ํ…์„œ ํ”„๋กœ๊ทธ๋žจ์„ ์œ„ํ•œ ์ €์ˆ˜์ค€ ์ถ”์ƒํ™”์ด๋ฉฐ, ๋‘ ๋ชจ๋“ˆ๋กœ ๋‚˜๋‰œ๋‹ค:

  • tirx (Tensor IR eXtensions): PrimFunc, Buffer, SBlock, ํ‘œํ˜„์‹, ๋ฌธ์žฅ ๋“ฑ ์ฝ”์–ด IR ์ •์˜์™€ ๋กœ์–ด๋ง ํŒจ์Šค๋ฅผ ๋‹ด๋‹นํ•œ๋‹ค.
  • s_tir (Schedulable TIR): ์Šค์ผ€์ค„ ํ”„๋ฆฌ๋ฏธํ‹ฐ๋ธŒ, MetaSchedule, DLight, ํ…์„œ ์ธํŠธ๋ฆฐ์‹œํฌ๋ฅผ ๋‹ด๋‹นํ•œ๋‹ค.

TensorIR์˜ ํ•ต์‹ฌ ์š”์†Œ๋Š” Block์ด๋‹ค. Block์€ ๋ฐ˜๋ณต๋ฌธ ๊ฒน์นจ(loop nest) ๋‚ด์—์„œ์˜ ๊ณ„์‚ฐ ๋‹จ์œ„๋ฅผ ๋‚˜ํƒ€๋‚ด๋ฉฐ, read/write region, ๋ฐ˜๋ณต๋ฌธ ์ถ•(axis) ์†์„ฑ, ๊ณ„์‚ฐ ์ฐจ์› ๋“ฑ ์Šค์ผ€์ค„๋ง์— ํ•„์š”ํ•œ ๊ตฌ์กฐ์  ์ •๋ณด๋ฅผ ๋ช…์‹œ์ ์œผ๋กœ ํฌํ•จํ•œ๋‹ค.

Relax

Relax๋Š” ML ๋ชจ๋ธ์˜ ๊ทธ๋ž˜ํ”„ ์ˆ˜์ค€ ์ถ”์ƒํ™”๋ฅผ ๋‹ด๋‹นํ•˜๋Š” ๊ณ ์ˆ˜์ค€ IR์ด๋‹ค. ํ•ต์‹ฌ ํŠน์ง•:

  • Dataflow Pattern Language (DPL): ํŒจํ„ด ๋งค์นญ๊ณผ ์žฌ์ž‘์„ฑ์„ ์œ„ํ•œ ์–ธ์–ด. ์—ฐ์‚ฐ ์œตํ•ฉ, ๊ทธ๋ž˜ํ”„ ๋ ˆ์ด์•„์›ƒ ์ตœ์ ํ™” ๋“ฑ์— ํ™œ์šฉ๋œ๋‹ค.
  • Graph-level Optimizations: Constant Folding, Dead Code Elimination, Operator Fusion
  • Cross-level Optimization: Relax์™€ TensorIR ๊ฐ„์˜ ๊ต์ฐจ ์ตœ์ ํ™”. LegalizeOps ํŒจ์Šค๋กœ Relax ์—ฐ์‚ฐ์„ TensorIR PrimFunc์œผ๋กœ ๋กœ์–ด๋งํ•˜๊ณ , FuseOps + FuseTIR๋กœ ์—ฌ๋Ÿฌ ์—ฐ์‚ฐ์„ ํ•˜๋‚˜์˜ ์ปค๋„๋กœ ์œตํ•ฉํ•œ๋‹ค.

๋น„๊ต/๋ถ„์„

TVM vs ๋‹ค๋ฅธ AI ์ปดํŒŒ์ผ๋Ÿฌ

ํ•ญ๋ชฉ TVM XLA TensorRT Glow
๊ฐœ๋ฐœ์‚ฌ Apache Google NVIDIA Meta
๋ผ์ด์„ ์Šค Apache 2.0 Apache 2.0 ๋…์  BSD
์ง€์› ํ•˜๋“œ์›จ์–ด ๋ฒ”์šฉ (GPU/CPU/NPU/TPU) TPU, GPU NVIDIA GPU GPU, NPU
์ž๋™ ํŠœ๋‹ MetaSchedule ์—†์Œ ์—†์Œ ์—†์Œ
ํ”„๋ ˆ์ž„์›Œํฌ ์ง€์› ONNX, PyTorch, TF, MXNet TensorFlow, JAX TensorRT ํŒŒ์„œ PyTorch, Caffe2
LLM ์ง€์› Relax + TIRx StableHLO TensorRT-LLM ์ œํ•œ์ 
๋ถ„์‚ฐ ์‹คํ–‰ Disco (NCCL/RCCL) TPU Pod ๋‚ด์žฅ ์ œํ•œ์ 

TVM ๋‚ด๋ถ€ ๋ชจ๋“ˆ ๋น„๊ต

๋ชจ๋“ˆ ์ถ”์ƒํ™” ์ˆ˜์ค€ ์—ญํ•  ๋Œ€์ƒ
Relax ๊ณ ์ˆ˜์ค€ ๊ทธ๋ž˜ํ”„ ๊ตฌ์กฐ, ์—ฐ์‚ฐ ์˜๋ฏธ ์—”๋“œํˆฌ์—”๋“œ ๋ชจ๋ธ
TensorIR ์ €์ˆ˜์ค€ ํ…์„œ ์ปค๋„, ๋ฃจํ”„/๋ฉ”๋ชจ๋ฆฌ ์ตœ์ ํ™” ๊ฐœ๋ณ„ ์—ฐ์‚ฐ/์œตํ•ฉ ์ปค๋„
MetaSchedule ์Šค์ผ€์ค„๋ง ๊ฒ€์ƒ‰ ๊ธฐ๋ฐ˜ ์ž๋™ ํŠœ๋‹ TensorIR ์ปค๋„
DLight ์Šค์ผ€์ค„๋ง ๊ทœ์น™ ๊ธฐ๋ฐ˜ GPU ์Šค์ผ€์ค„๋ง TensorIR ์ปค๋„
TOPI ๋„๋ฉ”์ธ ์‚ฌ์ „ ์ •์˜ ํ…์„œ ์—ฐ์‚ฐ ์ปค๋„ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ

์ •๋ฐ€๋„ ์ง€์› ๋น„๊ต

์ •๋ฐ€๋„ TVM ์ง€์› ์„ค๋ช…
FP32 O ๊ธฐ๋ณธ ์ •๋ฐ€๋„
FP16 O ํ•˜์ด๋ธŒ๋ฆฌ๋“œ ์ •๋ฐ€๋„, Mixed Precision
BF16 O Brain Floating Point, LLM ํ•™์Šต
FP8 O H100/H200 ์ง€์›, E4M3/E5M2
INT8 O ์–‘์žํ™” ์ถ”๋ก 
INT4 O 2๋น„ํŠธ/4๋น„ํŠธ ์–‘์žํ™”
FP4 O NVIDIA Blackwell ์ง€์›

๋™์ž‘ ์›๋ฆฌ

TVM ์ปดํŒŒ์ผ๋Ÿฌ ํŒŒ์ดํ”„๋ผ์ธ

TVM Compilation Pipeline
  1. ๋ชจ๋ธ ์ž„ํฌํŠธ ๋‹จ๊ณ„:
    - ํ”„๋ ˆ์ž„์›Œํฌ๋ณ„ ํ”„๋ก ํŠธ์—”๋“œ(Frontend)๊ฐ€ ๋ชจ๋ธ์„ ๋กœ๋“œํ•œ๋‹ค
    - ONNX: onnx.load() โ†’ relax.frontend.onnx.from_onnx()
    - PyTorch: torch.jit.trace() โ†’ relax.frontend.torch.from_fx()
    - ํ”„๋ ˆ์ž„์›Œํฌ ์ค‘๊ฐ„ ํ‘œํ˜„์„ Relax IR๋กœ ๋ณ€ํ™˜ํ•œ๋‹ค

  2. Relax ๊ทธ๋ž˜ํ”„ ์ตœ์ ํ™” ๋‹จ๊ณ„:
    - Constant Folding: ์ปดํŒŒ์ผ ์‹œ์ ์— ์ƒ์ˆ˜ ์—ฐ์‚ฐ ์ˆ˜ํ–‰
    - Dead Code Elimination: ๋ถˆํ•„์š”ํ•œ ์—ฐ์‚ฐ ์ œ๊ฑฐ
    - ** FuseOps: ์—ฐ์‚ฐ์„ ํŒจํ„ด ๊ธฐ๋ฐ˜์œผ๋กœ ์œตํ•ฉ ๋‹จ์œ„๋กœ ๋ถ„๋ฆฌ
    -
    LegalizeOps**: Relax ์—ฐ์‚ฐ์„ TensorIR PrimFunc์œผ๋กœ ๋กœ์–ด๋ง

  3. TensorIR ์Šค์ผ€์ค„๋ง ๋‹จ๊ณ„:
    - DLight (๊ทœ์น™ ๊ธฐ๋ฐ˜): ๋ฏธ๋ฆฌ ์ •์˜๋œ ๊ณ ์„ฑ๋Šฅ ์Šค์ผ€์ค„ ๊ทœ์น™ ์ ์šฉ

    • Tiling: ๋ฃจํ”„๋ฅผ ํƒ€์ผ๋กœ ๋ถ„ํ• ํ•˜์—ฌ ์บ์‹œ ์ ‘๊ทผ ์ตœ์ ํ™”
    • Vectorization: SIMD ๋ช…๋ น์–ด ํ™œ์šฉ
    • Thread Binding: GPU ์Šค๋ ˆ๋“œ ํ• ๋‹น
    • MetaSchedule (๊ฒ€์ƒ‰ ๊ธฐ๋ฐ˜): ์‹ค์ œ ์„ฑ๋Šฅ ์ธก์ • ๊ธฐ๋ฐ˜ ์ตœ์  ์กฐํ•ฉ ํƒ์ƒ‰
    • ๊ณต๊ฐ„ ํƒ์ƒ‰(Space Explorer) + ์„ฑ๋Šฅ ์˜ˆ์ธก(Performance Model)
  4. TensorIR ๋กœ์–ด๋ง ๋‹จ๊ณ„:
    - ๋ฉ€ํ‹ฐ์ฐจ์› ์ ‘๊ทผ์„ 1์ฐจ์› ํฌ์ธํ„ฐ ์ ‘๊ทผ์œผ๋กœ ํ‰ํƒ„ํ™”
    - ํ•˜๋“œ์›จ์–ด ํŠนํ™” ์ธํŠธ๋ฆฐ์‹œํฌ๋กœ ๋ณ€ํ™˜
    - ๋Ÿฐํƒ€์ž„ ํ˜ธ์ถœ ๊ทœ์•ฝ ์ถฉ์กฑ ํ•จ์ˆ˜ ์—”ํŠธ๋ฆฌ ๋ฐ์ฝ”๋ ˆ์ด์…˜

  5. ๋Œ€์ƒ ๋ฒˆ์—ญ(Target Translation) ๋‹จ๊ณ„:
    - LLVM IRBuilder๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ x86/ARM ๊ธฐ๊ณ„์–ด ์ƒ์„ฑ
    - CUDA C, OpenCL ์†Œ์Šค ์ฝ”๋“œ ์ƒ์„ฑ
    - BYOC(Bring Your Own Codegen)๋กœ cuBLAS, CUTLASS, cuDNN ๋“ฑ ์™ธ๋ถ€ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ๋””์ŠคํŒจ์น˜

  6. ๋Ÿฐํƒ€์ž„ ์‹คํ–‰ ๋‹จ๊ณ„:
    - runtime.Module์œผ๋กœ ์ปดํŒŒ์ผ ๊ฒฐ๊ณผ๋ฅผ ์บก์Аํ™”
    - PackedFunc์œผ๋กœ ํƒ€์ž… ์ œ๊ฑฐ๋œ ํ•จ์ˆ˜ ์ธํ„ฐํŽ˜์ด์Šค ์ œ๊ณต
    - Python, C++, Rust, Go, Java, JavaScript ๋“ฑ ๋‹ค์–‘ํ•œ ์–ธ์–ด์—์„œ ํ˜ธ์ถœ ๊ฐ€๋Šฅ

๋Ÿฐํƒ€์ž„ ์•„ํ‚คํ…์ฒ˜

TVM ๋Ÿฐํƒ€์ž„์€ ๋‹ค์Œ ํ•ต์‹ฌ ๊ตฌ์กฐ๋กœ ๊ตฌ์„ฑ๋œ๋‹ค:

๊ตฌ์กฐ ์„ค๋ช…
runtime.Module ์ปดํŒŒ์ผ ๊ฒฐ๊ณผ๋ฌผ์„ ์บก์Аํ™”. .so, .dll, .dylib ๋“ฑ์œผ๋กœ ๋‚ด๋ณด๋‚ด๊ธฐ
PackedFunc ํƒ€์ž… ์ œ๊ฑฐ๋œ ํ•จ์ˆ˜ ์ธํ„ฐํŽ˜์ด์Šค. POD ํƒ€์ž…, ๋ฌธ์ž์—ด, Tensor, Module, Function์„ ์ธ์ž๋กœ ๋ฐ›์Œ
runtime.Tensor ํ•˜๋“œ์›จ์–ด ๋ฉ”๋ชจ๋ฆฌ์— ์œ„์น˜ํ•œ ํ…์„œ ๋ž˜ํผ
Relax VM ๋ ˆ์ง€์Šคํ„ฐ ๊ธฐ๋ฐ˜ ์ธํ„ฐํ”„๋ฆฌํ„ฐ. Call, Ret, Goto, If ๋„ค ๊ฐ€์ง€ ์˜ต์ฝ”๋“œ๋กœ ์ œ์–ด ํ๋ฆ„ ์ฒ˜๋ฆฌ
Disco ๋ถ„์‚ฐ ์‹คํ–‰ ๋Ÿฐํƒ€์ž„. NCCL/RCCL์„ ํ†ตํ•œ allreduce, allgather ๋“ฑ ์ง‘ํ•ฉ ์—ฐ์‚ฐ ์ง€์›

Disco ๋ถ„์‚ฐ ๋Ÿฐํƒ€์ž„

Disco๋Š” ๋ชจ๋ธ์ด ๋‹จ์ผ GPU์— ๋“ค์–ด๊ฐ€์ง€ ์•Š์„ ๋•Œ ์‚ฌ์šฉ๋˜๋Š” ๋ถ„์‚ฐ ์‹คํ–‰ ๋Ÿฐํƒ€์ž„์ด๋‹ค. ํ•ต์‹ฌ ๊ฐœ๋…:

  • Session: ์›Œ์ปค ๊ทธ๋ฃน์„ ์†Œ์œ ํ•˜๊ณ  SPMD ์Šคํƒ€์ผ ํ”„๋กœ๊ทธ๋ž˜๋ฐ ์ธํ„ฐํŽ˜์ด์Šค๋ฅผ ์ œ๊ณตํ•œ๋‹ค
  • DRef: ์›Œ์ปค์— ์ƒ์ฃผํ•˜๋Š” ๋ถ„์‚ฐ ์ฐธ์กฐ. ๊ฐ ์›Œ์ปค์˜ ๋กœ์ปฌ ์ƒค๋“œ์— ๋Œ€์‘ํ•œ๋‹ค
  • ์„ธ ๊ฐ€์ง€ ์„ธ์…˜ ๋ฐฑ์—”๋“œ:
  • ThreadedSession: ๋‹จ์ผ ๋จธ์‹  ๋ฉ€ํ‹ฐGPU ์ถ”๋ก ์šฉ (๊ฐ€์žฅ ์ผ๋ฐ˜์ )
  • ProcessSession: ํ”„๋กœ์„ธ์Šค ๊ฒฉ๋ฆฌ๊ฐ€ ํ•„์š”ํ•œ ๊ฒฝ์šฐ
  • SocketSession: ๋ฉ€ํ‹ฐ๋…ธ๋“œ ํด๋Ÿฌ์Šคํ„ฐ์šฉ TCP ์†Œ์ผ“ ์—ฐ๊ฒฐ

MetaSchedule ์ž๋™ ํŠœ๋‹

MetaSchedule์€ TensorIR ์ปค๋„์˜ ์ตœ์  ์Šค์ผ€์ค„์„ ๊ฒ€์ƒ‰ ๊ธฐ๋ฐ˜์œผ๋กœ ์ฐพ๋Š” ํ”„๋ ˆ์ž„์›Œํฌ์ด๋‹ค.

์ž‘๋™ ๋ฐฉ์‹:
1. ํŠœ๋‹ ๊ฐ€๋Šฅํ•œ ์ž‘์—…(Tunable Task) ์ถ”์ถœ
2. ํƒ์ƒ‰ ๊ณต๊ฐ„(Space) ์ •์˜: Tiling ํฌ๊ธฐ, ๋ฒกํ„ฐํ™” ๊ธธ์ด, ์Šค๋ ˆ๋“œ ๋ฐฐ์น˜ ๋“ฑ
3. ์ƒ˜ํ”Œ๋ง ๋ฐ ์„ฑ๋Šฅ ์ธก์ •: ํ›„๋ณด ์Šค์ผ€์ค„์„ ์‹ค์ œ ํ•˜๋“œ์›จ์–ด์—์„œ ์‹คํ–‰
4. ๋ฐ์ดํ„ฐ๋ฒ ์ด์Šค ์ €์žฅ: ์ตœ์  ๊ฒฐ๊ณผ๋ฅผ ์žฌ์‚ฌ์šฉ ๊ฐ€๋Šฅํ•œ ํ˜•ํƒœ๋กœ ์ €์žฅ

DLight vs MetaSchedule:
- DLight: ๊ทœ์น™ ๊ธฐ๋ฐ˜. ๋น ๋ฅด๊ณ  ์•ˆ์ •์ ์ด๋ฉฐ, ๋ฒ”์šฉ GPU ์Šค์ผ€์ค„์— ์ ํ•ฉํ•˜๋‹ค
- MetaSchedule: ๊ฒ€์ƒ‰ ๊ธฐ๋ฐ˜. ๋А๋ฆฌ์ง€๋งŒ ๋” ๋‚˜์€ ์„ฑ๋Šฅ์„ ์ฐพ์„ ์ˆ˜ ์žˆ์œผ๋ฉฐ, ํŠน์ • ํ•˜๋“œ์›จ์–ด/์›Œํฌ๋กœ๋“œ์— ์ตœ์ ํ™”ํ•  ๋•Œ ์œ ์šฉํ•˜๋‹ค

์žฅ๋‹จ์ 

TVM ์žฅ๋‹จ์ 

์žฅ์  ๋‹จ์ 
๋ฒ”์šฉ ํ•˜๋“œ์›จ์–ด ์ง€์› (GPU, CPU, NPU, TPU) ํ•™์Šต ๊ณก์„ ์ด ๋†’์Œ
์˜คํ”ˆ์†Œ์Šค ์ปค๋ฎค๋‹ˆํ‹ฐ (Apache ์žฌ๋‹จ) ๋Œ€๊ทœ๋ชจ ๋ชจ๋ธ ์ง€์› ์‹œ ์ปดํŒŒ์ผ ์‹œ๊ฐ„ ๊น€
MetaSchedule ์ž๋™ ํŠœ๋‹ ๋ณต์žกํ•œ ๋””๋ฒ„๊น… ํ•„์š”
BYOC๋กœ ๋ฒค๋” ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ ํ†ตํ•ฉ ์ผ๋ถ€ ์ตœ์‹  ํ•˜๋“œ์›จ์–ด ์ง€์› ์ง€์—ฐ
TVMScript๋กœ ์ง๊ด€์  IR ๊ธฐ์ˆ  ๋ฉ”๋ชจ๋ฆฌ ์‚ฌ์šฉ๋Ÿ‰์ด ๋งŽ์Œ
๋ถ„์‚ฐ ์‹คํ–‰ ์ง€์› (Disco) ๋Ÿฐํƒ€์ž„ ์„ฑ๋Šฅ์ด ์ˆ˜๋™ ์ตœ์ ํ™” ๋Œ€๋น„ ์—ด์„ธ ๊ฐ€๋Šฅ
Relax + TensorIR ๊ต์ฐจ ์ตœ์ ํ™” ์ปค๋ฎค๋‹ˆํ‹ฐ ๊ธฐ์—ฌ ๊ฐ€์ด๋“œ๊ฐ€ ๋ณต์žกํ•จ
MLIR ํ˜ธํ™˜์„ฑ ์ถ”๊ตฌ ์—”ํ„ฐํ”„๋ผ์ด์ฆˆ ์ง€์› ๋ถ€์กฑ

TVM ์‚ฌ์šฉ ์‹œ ๊ณ ๋ ค์‚ฌํ•ญ

์ƒํ™ฉ ๊ถŒ์žฅ ์„ ํƒ
๋‹ค์–‘ํ•œ ํ•˜๋“œ์›จ์–ด ํƒ€๊ฒŸ์ด ํ•„์š”ํ•œ ๊ฒฝ์šฐ TVM
NVIDIA GPU ์ถ”๋ก ๋งŒ ํ•„์š”ํ•œ ๊ฒฝ์šฐ TensorRT
TensorFlow/JAX + TPU ์‚ฌ์šฉ ์‹œ XLA
์‹ค์‹œ๊ฐ„ ์ถ”๋ก  ์„ฑ๋Šฅ์ด ์ตœ์šฐ์„ ์ธ ๊ฒฝ์šฐ TensorRT ๋˜๋Š” ์ˆ˜๋™ ์ตœ์ ํ™”
์—ฐ๊ตฌ์šฉ ํ”„๋กœํ† ํƒ€์ดํ•‘ TVM (MetaSchedule ํ™œ์šฉ)
์—ฃ์ง€ ๋””๋ฐ”์ด์Šค ๋ฐฐํฌ TVM (ํฌ๋กœ์Šค ์ปดํŒŒ์ผ + RPC)

๊ด€๋ จ ๊ธฐ์ˆ 

๊ด€๋ จ ๋ฌธ์„œ

์ฐธ๊ณ  ๋ฌธํ—Œ

  • Chen et al., "TVM: An Automated End-to-End Optimizing Compiler for Deep Learning," OSDI 2018
  • Chen et al., "Learning to Optimize Tensor Programs," NeurIPS 2018
  • Shen et al., "A Flexible Approach to Autotuning for Deep Learning Compiler," MLSys 2021
  • Apache TVM Documentation: https://tvm.apache.org/docs/
  • Apache TVM GitHub Repository: https://github.com/apache/tvm
  • Relax Deep Dive: https://tvm.apache.org/docs/deep_dive/relax/index.html
  • TensorIR Deep Dive: https://tvm.apache.org/docs/deep_dive/tensor_ir/index.html
  • TIRx Overview: https://tvm.apache.org/docs/tirx/overview.html

ํ•ต์‹ฌ ์ •๋ฆฌ

  1. Apache TVM์€ ์˜คํ”ˆ์†Œ์Šค ๋”ฅ ๋Ÿฌ๋‹ ์ปดํŒŒ์ผ๋Ÿฌ ์Šคํƒ์œผ๋กœ, ๋‹ค์–‘ํ•œ ํ•˜๋“œ์›จ์–ด(GPU, CPU, NPU, TPU)์—์„œ ๊ณ ์„ฑ๋Šฅ ML ์‹คํ–‰์„ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜๋ฉฐ Apache ์žฌ๋‹จ ์‚ฐํ•˜์—์„œ ํ™œ๋ฐœํžˆ ๊ฐœ๋ฐœ๋˜๊ณ  ์žˆ๋‹ค
  2. ์ตœ์‹  TVM์€ Relax(๊ณ ์ˆ˜์ค€ ๊ทธ๋ž˜ํ”„ IR)์™€ TensorIR(์ €์ˆ˜์ค€ ํ…์„œ IR)์˜ ์ด์ค‘ IR ๊ตฌ์กฐ๋ฅผ ์ฑ„ํƒํ•˜์—ฌ ์—”๋“œํˆฌ์—”๋“œ ๊ต์ฐจ ์ตœ์ ํ™”๋ฅผ ์ง€์›ํ•˜๋ฉฐ, TVMScript๋กœ ์ง๊ด€์ ์ธ IR ๊ธฐ์ˆ ์ด ๊ฐ€๋Šฅํ•˜๋‹ค
  3. MetaSchedule(๊ฒ€์ƒ‰ ๊ธฐ๋ฐ˜)์™€ DLight(๊ทœ์น™ ๊ธฐ๋ฐ˜) ์ž๋™ ํŠœ๋‹์„ ํ†ตํ•ด ํ•˜๋“œ์›จ์–ด ํŠนํ™” ์ตœ์ ํ™”๋ฅผ ์ž๋™ํ™”ํ•˜๋ฉฐ, BYOC๋กœ cuBLAS, CUTLASS ๋“ฑ ์™ธ๋ถ€ ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋„ ํ†ตํ•ฉํ•  ์ˆ˜ ์žˆ๋‹ค
  4. Disco ๋ถ„์‚ฐ ๋Ÿฐํƒ€์ž„์€ NCCL/RCCL ๊ธฐ๋ฐ˜ ๋ฉ€ํ‹ฐGPU/๋ฉ€ํ‹ฐ๋…ธ๋“œ ์‹คํ–‰์„ ์ง€์›ํ•˜๋ฉฐ, Relax VM์€ ๋ ˆ์ง€์Šคํ„ฐ ๊ธฐ๋ฐ˜ ์ธํ„ฐํ”„๋ฆฌํ„ฐ๋กœ ์—”๋“œํˆฌ์—”๋“œ ๋ชจ๋ธ ์‹คํ–‰์„ ๋‹ด๋‹นํ•œ๋‹ค
  5. TVM์˜ ์ฃผ์š” ๊ฐ•์ ์€ ๋ฒ”์šฉ ํ•˜๋“œ์›จ์–ด ์ง€์›๊ณผ ์ž๋™ ํŠœ๋‹ ๊ธฐ๋Šฅ์ด๋ฉฐ, ๋‹จ์ ์€ ํ•™์Šต ๊ณก์„ ๊ณผ ์ปดํŒŒ์ผ ์‹œ๊ฐ„์ด๋‹ค